This invention relates to a semiconductor device and a fabrication technology thereof. More particularly, this invention relates to a technology that will be effective when applied to semiconductor memory devices having a DRAM (Dynamic Random Access Memory).
Memory cells of the DRAM are arranged in matrix on a main plane of a semiconductor substrate and are positioned at points of intersections between a plurality of word lines and a plurality of bit lines. Each memory cell comprises one memory cell selecting MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information storing capacitance device (capacitor) connected in series with the MISFET. The memory cell selecting MISFET is formed in an active region encompassed by a device isolation region, and mainly comprises a gate oxide film, a gate electrode formed integrally with the word line and a pair of semiconductor regions that constitute the source and the drain. The bit line is disposed over the memory cell selecting MISFET and is electrically connected to one of the source and drain that are shared by two memory cell selecting MISFETs adjacent to each other in the extending direction of the bit line. The information storing capacitance device is likewise disposed over the memory cell selecting MISFET and is electrically connected to the other of the source and drain.
A DRAM having a COB (Capacitor-Over-Bitline) structure having an information storing capacitor disposed over a bit line increases its surface area by cylindrically processing the lower electrode (storing electrode) of the information storing capacitance device positioned over the bit line in order to make up for the loss of the quantity of the charge stored (Cs) resulting from scale-down of the memory cell, and forms a capacitance insulating film and an upper electrode (plate electrode) over the surface.
As the integration density of the devices increases and the cell area diminishes, cubic configuration of the capacitor is necessary to a certain extent in order to secure operation reliability of the capacitor formed in the memory cell array region as a semiconductor memory device in the memory cell having the COB structure. When the capacitor having such a cubic configuration is formed and then an inter-level insulating film is formed, a step or a difference of levels corresponding to the height of the capacitor develops between the memory cell region and the peripheral circuit region.
Such a step tends to become higher and higher as the integration density of DRAMs increases and predetermined capacitance must be secured. To improve the integration density of the DRAMs, the improvement in exposure accuracy of photolithography is required and the value of the focal length that is allowed for satisfying this requirement becomes severer and severer. The increase of the step and the drop of the margin of the exposure focus in photolithography incur the problem that the formation of wiring layers formed on the inter-level insulating film becomes difficult.
To cylindrically process the lower electrode as described above, the process steps gets much more complicated, and the structure which is simplified to maximum is required. However, such a simplified structure of the lower electrode cannot increase the surface area, and ends up with the opposite result to the reduction of the step described above.
One of the methods of avoiding the problem of such a cubic structure capacitor is described in xe2x80x9cApplied Physicsxe2x80x9d, Vol. 65, No. 11, pp.1106-1113, Nov. 10, 1996, published by the Society of Applied Physics. This paper proposes a technology of a so-called xe2x80x9cHSG (Hemispherical Silicon Grain)xe2x80x9d structure that coarsens the silicon surface of the lower electrode to form fine ruggedness and substantially increases the surface area without increasing the lower electrode size.
On the other hand, Japanese Patent Laid-Open No. 56155/1998 describes a technology for forming an amorphous silicon film before the formation of crystal nuclei in a method of forming the HSG structure, and Japanese Patent Laid-Open No. 298284/1997 or No. 204426/1994 describes a technology that forms a second amorphous silicon film not containing an impurity on a first amorphous silicon film containing an impurity, and forms the HSG structure in the second amorphous silicon film.
However, the technologies of the HSG structure described above are not free from the following problems. In other words, the occupying area of the lower electrode must be decreased with scale-down of the device size for satisfying the requirement for a higher integration density of DRAMs. In the case of the cylindrical lower electrode, in particular, it is necessary to reduce the inner diameter of the cylinder and to form with high accuracy granular silicon inside the very small cylinder. In other words, it becomes very difficult to control of the height (ruggedness) of granular silicon with the reduction of the thickness of the polycrystalline silicon thin film that constitutes the lower electrode.
As the thickness of the polycrystalline silicon thin film constituting the lower electrode is decreased, the resistance of the polycrystalline silicon film becomes higher, and it becomes more difficult to secure sufficient conductivity of the lower electrode. The problem of this high resistance becomes particularly remarkable because the thickness of the film portion after the growth of granular silicon becomes small.
The influences of the depletion layer of the capacitor electrode are another problem. If the impurity inside the lower electrode comprising the polycrystalline silicon film is not sufficiently activated, or if the amount of the impurity is not sufficient, the carrier concentration drops, and the depletion layer develops in the lower electrode on the interface with the capacitance insulating film depending on the potential relationship with the upper electrode. The depletion layer, if it develops, substantially increases the film thickness of the capacitance insulating film by the thickness corresponding to its effective film thickness, and eventually invites the drop of the capacitance value. In the case of the HSG structure, in particular, the high impurity concentration impedes the growth of granular silicon, and the impurity concentration is likely to be insufficient after the growth of granular silicon. In consequence, the problem of the depletion layer is more likely to get actualized.
It is therefore an object of the present invention to provide a technology capable of controlling the film thickness of a polycrystalline silicon film applied to a capacitor lower electrode, inclusive of the granular silicon portion (rugged portion).
It is another object of the present invention to provide a technology capable of controlling the height (ruggedness) of granular silicon on the surface of the polycrystalline silicon film.
It is another object of the present invention to provide a technology capable of preventing the increase of the resistance of the polycrystalline silicon film applied to the capacitor lower electrode and securing conductivity of the lower electrode.
It is still another object of the present invention to provide a technology capable of preventing the occurrence of a depletion layer (depletion) of the polycrystalline silicon film at the boundary between the polycrystalline silicon film constituting the capacitor lower electrode and the capacitance insulating film, and suppressing the drop of a stored capacitance due to depletion.
The above and other objects and novel features of the present invention will become more apparent from the following description of the specification and the accompanying drawings.
The following will illustrate typical examples of the inventions disclosed in this application.
According to one aspect of the present invention, the first electrode that constitutes a capacitance device comprises a silicon film having a substantially equal film thickness and a granular silicon crystal on the surface of the silicon film. Therefore, the resistance of the first electrode can be reduced.
According to another aspect of the present invention, a granular silicon crystal is formed by supplying silicon from an amorphous silicon film formed on the silicon film when a first electrode constituting a capacitance device is formed. In this instance, the supply of silicon is made only from amorphous silicon but not from the silicon film. Therefore, the height of the granular silicon crystal and its grain size can be easily controlled.
According to still another aspect of the present invention, the silicon film does not contribute to the formation of the granular silicon crystal. Therefore, a silicon film having a high impurity concentration can be employed, and the resistance of the first electrode can be lowered.
According to still another aspect of the present invention, a silicon film having a high impurity concentration can be employed, and depletion of the first electrode can be reduced. Therefore, the drop of the stored capacitance can be prevented.
According to still another aspect of the present invention, the formation condition of the crystal grains becomes easier by forming the granular silicon crystal by using amorphous silicon containing an impurity in a low concentration.